1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory, and to a method for reading data from the nonvolatile semiconductor memory. More particularly, the present invention relates to a nonvolatile semiconductor memory of a charge trapping-type, and to a method for reading data from the nonvolatile semiconductor memory of the charge trapping-type.
2. Description of Related Art
Flash memories and charge trapping memories are known as “electrically erasable/rewritable nonvolatile semiconductor memories.” Among them, charge trapping memories store data by using devices which trap charge. For example, metal oxide nitride oxide silicon (MONOS) transistors are charge trapping devices. The MONOS transistors are a kind of metal insulator silicon (MIS) transistors and use, as their gate insulating film, an oxide nitride oxide (ONO) film which has a silicon oxide, a silicon nitride and a silicon oxide film stacked in this order.
The silicon nitride film of the ONO film has a property to trap charge. For example, electrons can be injected into the silicon nitride film by applying an adequate electric potential to the gate electrode, source/drain and substrate. When electrons are trapped in the silicon nitride film, the threshold voltage of the MONOS transistor is larger than when electrons are not trapped. Conversely, when the trapped electrons are pulled out of the silicon nitride film, the threshold voltage decreases. Taking advantage of such change in the threshold voltage, the MONOS transistor can store data “1” and “0” in a nonvolatile manner. In other words, the charge trapping memory stores data by using the MONOS transistor as a memory cell transistor.
A conventional charge trapping memory (TwinMONOS) exists in which one memory cell has two MONOS transistors. Two control gates are formed on both sides of a word gate and an ONO film is formed between each control gate and a substrate. In other words, two MONOS transistors are formed on both sides of a word gate and one memory cell can record 2-bit data. When reading data, the 2-bit data are classified into bits to be read and the other bits. Hereinafter, the control gate for the bits to be read is referred to as “read CG” and the other control gate is referred to as an “override CG.”
Data reading in the conventional charge trapping memory is divided into a standby stage and a reading stage. In the standby stage, the read CG and override CG are each precharged to a power supply potential (1.8 V). The potential applied to the word gate is 0 V. In the subsequent reading stage, while the read CG remains electrically connected to the power supply, the override CG is set to a floating state. Furthermore, power supply potential (1.8 V) is applied to the word gate. At this time, since the read CG remains electrically connected to the power supply, its potential remains 1.8 V. On the other hand, the potential of the override CG in the floating state is boosted to approximately 2.5 V due to capacitive coupling with the word gate.